UDP Offload in FPGA - Milpitas




About

We provide TCP offload NIC in FPGA, TCP Acceleration is the technique that helps to achieve much better throughput and goodput of Internet connection link.


More Detail

Whether you are looking for the TOE in Kernel Bypass or UDP Offload in FPGA, get all of the benefits of UDP Acceleration and TCP/IP offload engine for thousands of Sessions over.

Services

Jump-start your design

Intilop has several groups who can take on projects that range from a small 100k Gate FPGA design/integration to 10 M gate SOC Design/integration/Verification project or a small 2 inch X 2 inch board for an embedded design application to 22 inch X 26 inch, 24 layer multi-Giga bit blade server Board with multiple 1000+ pin BGA devices. In addition they can develop full scale firmware that ranges from developing en embedded RTOS to various device drivers to full scale enterprise software. They offer full turnkey hardware and software design capability. 
For example, over the years the team at intilop has:

 

  • Developed, or done a significant part of design/verification of, and taped out more that 30 SOCs, complex ASICs and FPGAs. Some of them integrated more than 24 different IP blocks and multiple processors, more than 6 million gates running at 500 MHz in 90 nm technology library. Some utilized the largest SoC-FPGAs available from Xilinx and Altera in V2, V4, V5 families.
     
  • Has developed 42 different boards of various complexities involving the latest technology interfaces designing around multiple CPUs, Multiple Network and data processing devices, various memory and I/O interfaces and technologies. 
     
  • Has developed RTOS and hundreds of various software driver modules.
     


In the area of SoC/ASIC/FPGA-SOC:

  • System level modeling, Planning and Specification development
  • IP integration, IP evaluation
  • Micro-architecture and design specification
  • Verification methodology, plan and tests cases development
  • RTL Design and Verification
  • Property checking, model checking and assertions
  • System and RTL co-simulation
  • Synthesis and STA
  • Gate level Verification
  • Front and Back end Design For Test (DFT ) Services
  • Floor Planning, Power planning, Place & Route, and Timing Closure
  • Formal Verification and Equivalency Checking
  • Physical verification and tape out


In the area of Board/System design:

  • Develop system level specifications
  • Identify functions, sub-functions
  • Hardware software tradeoffs
  • Partition design, research/select components
  • Cary out board design through all phases: Schematics to PCB
  • Bring up/debug/test boards
  • Firmware, Device Driver, RTOS integration


List of Design Services Projects 

Some of the application areas have been:

  • Network Security
  • Network Infrastructure
  • Data Security, SAN. NAS
  • High end consumer appliances
  • Miscellaneous embedded hardware and software applications

 

 


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